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1/11 october 2002 n high speed: t pd = 5.0 ns (typ.) at v cc =5v n low power dissipation: i cc =4 m a (max.) at t a =25c n high noise immunity: v nih =v nil = 28% v cc (min.) n power down protection on inputs n symmetrical output impedance: |i oh |=i ol =8ma(min) n balanced propagation delays: t plh @ t phl n operating voltage range: v cc (opr) = 2v to 5.5v n pin and function compatible with 74 series 573 n improved latch-up immunity n low noise: v olp = 0.9v (max.) description the 74vhc573 is an advanced high-speed cmos octal d-type latch with 3 state outputs non inverting fabricated with sub-micron silicon gate and double-layer metal wiring c 2 mos technology. these8bitd-typelatcharecontrolledbyalatch enable input (le) and an output enable input (oe ). while the le inputs is held at a high level, the q outputs will follow the data input precisely . when the le is taken low, the q outputs will be latched precisely at the logic level of d input data. while the (oe ) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and while (oe ) is in high level, the outputs will be in a high impedance state. power down protection is provided on all inputs and 0 to 7v can be accepted on inputs with no regard to the supply voltage. this device can be used to interface 5v to 3v. all inputs and outputs are equipped with protection circuits against static discharge, giving them 2kv esd immunity and transient excess voltage. 74vhc573 octal d-type latch with 3 state outputs non inverting pin connection and iec logic symbols order codes package tube t & r sop 74vhc573m 74VHC573MTR tssop 74vhc573ttr tssop sop
74vhc573 2/11 input equivalent circuit pin description truth table x : dont care z : high impedance * : q outputs are latched at the time when the le input is taken low logic level logic diagram this logic diagram has not be used to estimate propagation delays pin no symbol name and function 1oe 3 state output enable input (active low) 2, 3, 4, 5, 6, 7, 8, 9 d0 to d7 data inputs 12, 13, 14, 15, 16, 17, 18, 19 q0 to q7 3-state latch outputs 11 le latch enable input 10 gnd ground (0v) 20 v cc positive supply voltage inputs output oe le d q hxxz l l x no change* lhll lhhh
74vhc573 3/11 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied recommended operating conditions 1) v in from 30% to 70% of v cc symbol parameter value unit v cc supply voltage -0.5 to +7.0 v v i dc input voltage -0.5 to +7.0 v v o dc output voltage -0.5 to v cc + 0.5 v i ik dc input diode current -20 ma i ok dc output diode current 20 ma i o dc output current 25 ma i cc or i gnd dc v cc or ground current 75 ma t stg storage temperature -65 to +150 c t l lead temperature (10 sec) 300 c symbol parameter value unit v cc supply voltage 2 to 5.5 v v i input voltage 0 to 5.5 v v o output voltage 0 to v cc v t op operating temperature -55 to 125 c dt/dv input rise and fall time (note 1) (v cc =3.3 0.3v) (v cc = 5.0 0.5v) 0 to 100 0to20 ns/v
74vhc573 4/11 dc specifications symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v ih high level input voltage 2.0 1.5 1.5 1.5 v 3.0 to 5.5 0.7v cc 0.7v cc 0.7v cc v il low level input voltage 2.0 0.5 0.5 0.5 v 3.0 to 5.5 0.3v cc 0.3v cc 0.3v cc v oh high level output voltage 2.0 i o =-50 m a 1.9 2.0 1.9 1.9 v 3.0 i o =-50 m a 2.9 3.0 2.9 2.9 4.5 i o =-50 m a 4.4 4.5 4.4 4.4 3.0 i o =-4 ma 2.58 2.48 2.4 4.5 i o =-8 ma 3.94 3.8 3.7 v ol low level output voltage 2.0 i o =50 m a 0.0 0.1 0.1 0.1 v 3.0 i o =50 m a 0.0 0.1 0.1 0.1 4.5 i o =50 m a 0.0 0.1 0.1 0.1 3.0 i o =4 ma 0.36 0.44 0.55 4.5 i o =8 ma 0.36 0.44 0.55 ioz high impedance output leakage current 5.5 v i =v ih or v il v o =v cc or gnd 0.25 2.5 2.5 m a i i input leakage current 0to 5.5 v i = 5.5v or gnd 0.1 1 1 m a i cc quiescent supply current 5.5 v i =v cc or gnd 44040 m a
74vhc573 5/11 ac electrical characteristics (input t r =t f =3ns) (*) voltage range is 3.3v 0.3v (**) voltage range is 5.0v 0.5v note 1 : parameter guaranteed by design. t solh =|t plhm -t plhn |, t sohl =|t phlm -t phln | capacitive characteristics 1) c pd is defined as the value of the ics internal equivalent capacitance which is calculated from the operating current consumption without load. (refer to test circuit). average operating current can be obtained by the following equation. i cc(opr) =c pd xv cc xf in +i cc /8 (per latch) symbol parameter test condition value unit v cc (v) c l (pf) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. t plh t phl propagation delay time le to q 3.3 (*) 15 7.6 11.9 1.0 14.0 1.0 14.0 ns 3.3 (*) 50 10.1 15.4 1.0 17.5 1.0 17.5 5.0 (**) 15 5.0 7.7 1.0 9.0 1.0 9.0 5.0 (**) 50 6.5 9.7 1.0 11.0 1.0 11.0 t plh t phl propagation delay time dtoq 3.3 (*) 15 7.0 11.0 1.0 13.0 1.0 13.0 ns 3.3 (*) 50 9.5 14.5 1.0 16.5 1.0 16.5 5.0 (**) 15 4.5 6.8 1.0 8.0 1.0 8.0 5.0 (**) 50 6.0 8.8 1.0 10.0 1.0 10.0 t pzl t pzh output enable time 3.3 (*) 15 r l =1k w 7.3 11.5 1.0 13.5 1.0 13.5 ns 3.3 (*) 50 r l =1k w 9.8 15.0 1.0 17.0 1.0 17.0 5.0 (**) 15 r l =1k w 5.2 7.7 1.0 9.0 1.0 9.0 ns 5.0 (**) 50 r l =1k w 6.7 9.7 1.0 11.0 1.0 11.0 t plz t phz output disable time 3.3 (*) 50 r l =1k w 10.7 14.5 1.0 16.5 1.0 16.5 ns 5.0 (**) 50 r l =1k w 6.7 9.7 1.0 11 1.0 11 t w pulse width (le) high 3.3 (*) 5.0 5.0 5.0 ns 5.0 (**) 5.0 5.0 5.0 t s setup time d to le high or low 3.3 (*) 3.5 3.5 3.5 ns 5.0 (**) 3.5 3.5 3.5 t h setup time d to le high or low 3.3 (*) 1.5 1.5 1.5 ns 5.0 (**) 1.5 1.5 1.5 t oslh t oshl output to output skew time (note 1) 3.3 (*) 50 1.5 1.5 1.5 ns 5.0 (**) 50 1.0 1.0 1.0 symbol parameter test condition value unit t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. c in input capacitance 810 10 10pf c out output capacitance 10 pf c pd power dissipation capacitance (note 1) 29 pf
74vhc573 6/11 dynamic switching characteristics 1) worst case package. 2) max number of outputs defined as (n). data inputs are driven 0v to 5.0v, (n-1) outputs switching and one output at gnd. 3) max number of data inputs (n) switching. (n-1) switching 0v to 5.0v. inputs under test switching: 5.0v to threshold (v ild ), 0v to threshold (v ihd ), f=1mhz. test circuit c l =15/50pf or equivalent (includes jig and probe capacitance) r l =r1=1k w or equivalent r t =z out of pulse generator (typically 50 w ) symbol parameter test condition value unit v cc (v) t a = 25c -40 to 85c -55 to 125c min. typ. max. min. max. min. max. v olp dynamic low voltage quiet output (note 1, 2) 5.0 c l =50pf 0.6 0.9 v v olv -0.9 -0.6 v ihd dynamic high voltage input (note 1, 3) 5.0 3.5 v v ild dynamic low voltage input (note 1, 3) 5.0 1.5 v test switch t plh ,t phl open t pzl ,t plz v cc t pzh ,t phz gnd
74vhc573 7/11 waveform 1: le to qn propagation delays, le minimun pulse width, dn to le setup and hold times (f=1mhz; 50% duty cycle)
74vhc573 8/11 waveform 2: output enable and disable times (f=1mhz; 50% duty cycle) waveform 3: propagation delay time (f=1mhz; 50% duty cycle)
74vhc573 9/11 dim. mm. inch min. typ max. min. typ. max. a 2.65 0.104 a1 0.1 0.2 0.004 0.008 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.012 c 0.5 0.020 c1 45? (typ.) d 12.60 13.00 0.496 0.512 e 10.00 10.65 0.393 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.40 7.60 0.291 0.300 l 0.50 1.27 0.020 0.050 m 0.75 0.029 s ? (max.) so-20 mechanical data po13l 8
74vhc573 10/11 dim. mm. inch min. typ max. min. typ. max. a 1.2 0.047 a1 0.05 0.15 0.002 0.004 0.006 a2 0.8 1 1.05 0.031 0.039 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.0079 d 6.4 6.5 6.6 0.252 0.256 0.260 e 6.2 6.4 6.6 0.244 0.252 0.260 e1 4.3 4.4 4.48 0.169 0.173 0.176 e 0.65 bsc 0.0256 bsc k0? 8?0? 8? l 0.45 0.60 0.75 0.018 0.024 0.030 tssop20 mechanical data c e b a2 a e1 d 1 pin 1 identification a1 l k e 0087225c
74vhc573 11/11 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no res ponsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result f rom its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specificati ons mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devi ces or systems without express written approval of stmicroelectronics. ? the st logo is a registered trademark of stmicroelectronics ? 2002 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malt a - morocco singapore - spain - sweden - switzerland - united kingdom - united states. ? http://www.st.com

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